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Freescale Semiconductor /MKW31Z4 /RSIM_REGS /DSM_CONTROL

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Interpret as DSM_CONTROL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DSM_ANT_READY)DSM_ANT_READY 0 (ANT_DEEP_SLEEP_STATUS)ANT_DEEP_SLEEP_STATUS 0 (DSM_ANT_FINISHED)DSM_ANT_FINISHED 0 (ANT_SYSCLK_REQUEST_EN)ANT_SYSCLK_REQUEST_EN 0 (ANT_SLEEP_REQUEST)ANT_SLEEP_REQUEST 0 (ANT_SYSCLK_REQ)ANT_SYSCLK_REQ 0 (ANT_SYSCLK_INTERRUPT_EN)ANT_SYSCLK_INTERRUPT_EN 0 (ANT_SYSCLK_REQ_INT)ANT_SYSCLK_REQ_INT 0 (DSM_GEN_READY)DSM_GEN_READY 0 (GEN_DEEP_SLEEP_STATUS)GEN_DEEP_SLEEP_STATUS 0 (DSM_GEN_FINISHED)DSM_GEN_FINISHED 0 (GEN_SYSCLK_REQUEST_EN)GEN_SYSCLK_REQUEST_EN 0 (GEN_SLEEP_REQUEST)GEN_SLEEP_REQUEST 0 (GEN_SYSCLK_REQ)GEN_SYSCLK_REQ 0 (GEN_SYSCLK_INTERRUPT_EN)GEN_SYSCLK_INTERRUPT_EN 0 (GEN_SYSCLK_REQ_INT)GEN_SYSCLK_REQ_INT 0 (DSM_ZIG_READY)DSM_ZIG_READY 0 (ZIG_DEEP_SLEEP_STATUS)ZIG_DEEP_SLEEP_STATUS 0 (DSM_ZIG_FINISHED)DSM_ZIG_FINISHED 0 (ZIG_SYSCLK_REQUEST_EN)ZIG_SYSCLK_REQUEST_EN 0 (ZIG_SLEEP_REQUEST)ZIG_SLEEP_REQUEST 0 (ZIG_SYSCLK_REQ)ZIG_SYSCLK_REQ 0 (ZIG_SYSCLK_INTERRUPT_EN)ZIG_SYSCLK_INTERRUPT_EN 0 (ZIG_SYSCLK_REQ_INT)ZIG_SYSCLK_REQ_INT 0 (DSM_TIMER_CLR)DSM_TIMER_CLR 0 (DSM_TIMER_EN)DSM_TIMER_EN

Description

Deep Sleep Timer Control

Fields

DSM_ANT_READY

ANT Ready for Deep Sleep Mode
ANT_DEEP_SLEEP_STATUS

ANT Link Layer Deep Sleep Mode Status
DSM_ANT_FINISHED

ANT Deep Sleep Time Finished
ANT_SYSCLK_REQUEST_EN

Enable ANT Link Layer to Request RF OSC
ANT_SLEEP_REQUEST

ANT Link Layer Deep Sleep Requested
ANT_SYSCLK_REQ

ANT Link Layer RF OSC Request Status
ANT_SYSCLK_INTERRUPT_EN

ANT Link Layer RF OSC Request Interrupt Enable
ANT_SYSCLK_REQ_INT

Interrupt Flag from an ANT Link Layer RF OSC Request
DSM_GEN_READY

Generic FSK Ready for Deep Sleep Mode
GEN_DEEP_SLEEP_STATUS

Generic FSK Link Layer Deep Sleep Mode Status
DSM_GEN_FINISHED

Generic FSK Deep Sleep Time Finished
GEN_SYSCLK_REQUEST_EN

Enable Generic FSK Link Layer to Request RF OSC
GEN_SLEEP_REQUEST

Generic FSK Link Layer Deep Sleep Requested
GEN_SYSCLK_REQ

Generic FSK Link Layer RF OSC Request Status
GEN_SYSCLK_INTERRUPT_EN

Generic FSK Link Layer RF OSC Request Interrupt Enable
GEN_SYSCLK_REQ_INT

Interrupt Flag from an Generic FSK Link Layer RF OSC Request
DSM_ZIG_READY

802.15.4 Ready for Deep Sleep Mode
ZIG_DEEP_SLEEP_STATUS

802.15.4 Link Layer Deep Sleep Mode Status
DSM_ZIG_FINISHED

802.15.4 Deep Sleep Time Finished
ZIG_SYSCLK_REQUEST_EN

Enable 802.15.4 Link Layer to Request RF OSC
ZIG_SLEEP_REQUEST

802.15.4 Link Layer Deep Sleep Requested
ZIG_SYSCLK_REQ

802.15.4 Link Layer RF OSC Request Status
ZIG_SYSCLK_INTERRUPT_EN

802.15.4 Link Layer RF OSC Request Interrupt Enable
ZIG_SYSCLK_REQ_INT

Interrupt Flag from an 802.15.4 Link Layer RF OSC Request
DSM_TIMER_CLR

Deep Sleep Mode Timer Clear
DSM_TIMER_EN

Deep Sleep Mode Timer Enable

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data